Unix make
Last modified at 1:37 PM on 9/10/01

Typical Unix usage:

		make

make will look for its instructions in a file named makefile.

Assuming makefile exists, make starts with the first entry in the makefile file.
If make is given an argument, e.g.,

		make xyz
make searches the file for a target named xyz. and starts with that entry.


Each entry in makefile consists of:

The format of the dependency line is:

         target: [prerequisite1] [prerequisite2]...

If any prerequisites are given, they can be names of files or other targets in this makefile. Use spaces as separators, not tabs.

The format of a command line is:

Comment lines begin with a #


Starting with the prerequisites of the specified target, make follows the hierarchical tree of target / prerequisite entries until it gets to the lowest level. It works its way back up through this tree. If any entry along the tree has a target that is not at least as recent as all of its prerequisites, the commands for that entry are executed.

A common organization is to have an entry for the program name, with each of the object files that make up the program as prerequisites. The command(s) in this entry link the object files together.

Then there is an entry for each object file, with its source file and header file(s) as prerequisites. The command(s) in each of these entries compile the source file and produce the corresponding object file.

It is also common to have various utility targets in a makefile.

Example makefile:
# makefile to create myProg

myProg: myProg.o sub.o 
        gcc myProg.o sub.o -o myProg

myProg.o: myProg.c sub.h
        gcc -c -g myProg.c

sub.o: sub.c sub.h
        gcc -c -g sub.c

clean:
        rm *.o *~
Notes:
  1. Recall that if no target is specified, make will start with the first entry. So I have placed the final program target as the first entry.
  2. Since the clean target has no prerequisites, it can never be "at least as recent as all of its prerequsites." Thus
    			make clean
    	
    will always cause the command
    			rm *.o *~
    	
    to be executed.

These notes barely touch upon the capabilities of the Unix make utility. There are extensive macros, special variables, etc., etc. It is common to design makefiles that create a program from its source files, install all the configuration files, etc. in their proper locations, and remove object files and other temporary files. A good design would also include a utility target for removing the program, including all the configuration files.